Pulsic Adds Analog/Mixed-Signal Expert to U.S. Team
Karpinski Named Senior Applications Engineer
Bristol, UK – March 23, 2005 – Pulsic Ltd., the electronic design automation (EDA) company that delivers shape-based, integrated circuit (IC) physical design solutions for mixed-signal, memory and custom digital designs, has named analog, mixed-signal expert Peter Karpinski to its team in the United States.
Based in Denver, Karpinski is senior applications engineer and reports to Kirti Parmar, Pulsic’s applications director, North America. His responsibilities include pre- and post-sales support, developing tutorials, product demonstrations and workshops.
Notes Ken Roberts, chief executive officer at Pulsic: “Analog and mixed-signal expertise is uncommon, which is why we’re delighted that Peter accepted our offer.”
Karpinski joins Pulsic from Cadence Design Systems Inc. (NYSE: CDN) where he was employed from 1997 to the present as a senior applications engineer, supporting the Virtuoso product family for analog and mixed signal circuits. Previously, he worked for Cooper and Chyan Technology from 1993-1997 and served as application engineer, trainer, quality assurance engineer and sales manager before it was acquired by Cadence in 1997. Karpinski owned PC design company Ridge Designs Inc. from 1977 to 1993. He also worked as a PC designer for National Semiconductor and The Designers. He holds a Bachelor of Arts degree from the University of California in Santa Barbara.
“Pulsic is attracting attention in the market and winning customers worldwide,” adds Karpinski. “Its unique approach to analog and mixed-signal design intrigued me and convinced me to become part of the team.”
Pulsic’s Lyric Physical Design Framework offers detailed floorplanning, standard cell placement, interactive editing and automatic routing. Its unified shape-based design system has achieved significant design wins in the mixed signal, memory and custom digital market segments in the U.S., Europe and Asia by enabling layout designers to achieve high productivity and reduce die sizes by up to 30%, particularly as process geometries shrink.