CDA is a new class of EDA tool – pioneered and developed by Pulsic – that releases engineers from the constraints imposed by ASIC design styles and automates complex custom design layout to give you faster design, more accurate iteration and better optimal outcomes.
CDA brings together planning, placement and shape-based routing in a single hierarchical environment, enabling productivity boosts of up to 50% in custom layout to be realised.
Automating mixed signal design
CDA reverses the traditional ‘bottom up’ custom design approach – starting with leaf cells of transistors, followed by layer-on-layer of logic – with a ‘top-down’ approach that integrates timing-driven placement, intelligent floorplanning and hierarchy management.
Shaping up for profit
Today’s CDA architectures incorporate intelligent floorplanning, hierarchy management with timing-driven and specialised placement technologies (for example, super cluster placement) on a constraint-driven shape-based routing foundation to deliver dramatic results. A recent mixed-signal design – now in production – yielded a 25% area reduction and 20% less vias to improve yield.
In DRAM design, for example, CDA delivers – super cluster placement with spine and stitch routing – that resolves the commercial design challenge of minimising peripheral logic spine height.
From design to implementation
Homogenous and hierarchical constraint management across floorplanning, placement and routing means designers can set physical, electrical, object and inter-object relationships with constraints. Together with other design intents – such as clustering, timing, width, spacing or shielding – these can be set and held in the design environment and maintained throughout physical implementation.
Coping with change
A shape-based physical design platform also deals effectively with change, making it easy to assimilate new design rules and minimise the area impact of ECOs.
With shape-based CDA, the change process becomes both interactive and iterative and s can be performed locally (unlike grid-based routers which handle ECOs by performing large scale re-routing of the design).
Incremental routing capabilities significantly reduce the time to incorporate ECOs. Designers can stop automatic routing, make adjustments to the floorplan, routing costs or other rules – or even route a section by hand – before recommencing auto-routing.
“As a contributing member, Pulsic will have the opportunity to help evolve existing IPL Alliance standards and define emerging ones.”
Jingwen Yuan
President of the IPL Alliance
“Saifun provides flash designs to some of the world’s leading flash manufacturers. After carrying out a detailed evaluation, we chose the Pulsic solution as we believe it will provide us with significant productivity gains in relation to our unique and innovative NROM memory IP.”
Yoram Betser
Vice President of Design
Saifun Semiconductors Ltd.
“With Pulsic, we have a partner that delivers the features, the performance and most importantly the quality of results that meets our design and performance goals. Pulsic’s technology has become an important part of our design flow”
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Masaki Momodomi,
Technology Executive for flash memory,
Semiconductor Company,
Toshiba Corporation
“Pulsic has a strong reputation for customer-driven solutions, and their expanded efforts in interoperability come at an important time…”
Gary Smith
Chief Analyst
GarySmith EDA
“Pulsic provides a high quality handcrafted routing result. We have achieved at least a two-fold decrease in total layout turnaround time by using Unity for the routing phase alone.”
Ichiro Yamamoto
Senior Manager, Design System Department
Oki Electric Industry Co., Ltd