UniEdit™ gives you a fully featured interactive and semi-automatic editing environment for advanced analog IC design.
- Full support for sub 100nm process rules (end of line/short edge/fat wire/via adjacency) and high productivity nm routing tasks.
- Comprehensive ECO capacity.
- DFM friendly layouts that deliver high yields.
Interactive editing
UniEdit’s single, intuitive environment helps reduce time-to-market and improves overall management of the design process. Control cell placement, edit, and complete cell interconnects with ease ― and take advantage of design partitioning to enable several engineers to work concurrently on design layouts.
- DRC correct connectivity driven transistor level routing – manual, interactive and automatic.
- Integration with Cadence, CDBA and Open Access environments eliminates technology setup/design import issues.
- Persistent online DRC checking ensures manual operations are completed error-free, first time.
Advanced routing
UniEdit contains fully interactive and automatic connectivity-driven routing. Semi- automatic routing tools let you guide the routing engine around complex design areas and close-down troublesome nets.
- Comprehensive constraint management ensures constraints pass from schematic to the route driver.
- Online DRC checking.
- Push and Shove interactive routing, plus differential pair routing, shielding, matched routing, footprint routing, shielding and mirror and template routing.
Bespoke design capabilities
UniEdit’s tools support the implementation of incremental changes, enabling design re-entry and ECOs. Intelligent tools help automate improvements to circuit stability and yield, to deliver true bespoke-style design capability.
- Hierarchical constraint management enables control of all aspects of physical design including spacing, rules, widths, shielding, and electrical constraints.
- Device level floorplanning capabilities including alignment, placement in rows, and automatic block placement.
Optimized productivity
UniEdit provides support for high performance nm routing tasks, such as compaction, nm process support and constrained driven layout.
- Unique and fast automatic Well and guard ring creation.
- Intelligent editing.
- Dual control of path resistance and capacitance.
Testimonials
“Pulsic has a strong reputation for customer-driven solutions, and their expanded efforts in interoperability come at an important time…”
Gary Smith
Chief Analyst
GarySmith EDA
“Saifun provides flash designs to some of the world’s leading flash manufacturers. After carrying out a detailed evaluation, we chose the Pulsic solution as we believe it will provide us with significant productivity gains in relation to our unique and innovative NROM memory IP.”
Yoram Betser
Vice President of Design
Saifun Semiconductors Ltd.
“With Pulsic, we have a partner that delivers the features, the performance and most importantly the quality of results that meets our design and performance goals. Pulsic’s technology has become an important part of our design flow”
Masaki Momodomi,
Technology Executive for flash memory,
Semiconductor Company,
Toshiba Corporation
“As a contributing member, Pulsic will have the opportunity to help evolve existing IPL Alliance standards and define emerging ones.”
Jingwen Yuan
President of the IPL Alliance
“Pulsic provides a high quality handcrafted routing result. We have achieved at least a two-fold decrease in total layout turnaround time by using Unity for the routing phase alone.”
Ichiro Yamamoto
Senior Manager, Design System Department
Oki Electric Industry Co., Ltd
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